Integrated circuit (IC) chips are often electrically connected to package substrates in packaging assemblies to provide external signal exchange. A commonly used bonding scheme is flip-chip bonding. FIG. 1 schematically illustrates a flip-chip bonding structure, wherein IC chip 100 is bonded onto package substrate 102 through bump balls 104. It is commonly observed, however, that the coefficient of thermal expansion (CTE) of IC chip 100 is significantly different from that of package substrate 102. For example, the CTE of IC chip 100 may be about 3 ppm/° C., while the CTE of package substrate 102 may be about 15 ppm/° C. Due to the difference in CTEs, stresses are generated inside IC chip 100 and package substrate 102, resulting in warpage, as is schematically illustrated in FIG. 2.
The warpage results in the cracking of bump balls 104 and the delamination of low-k dielectric layers (not shown) in IC chip 100. Currently, many processes use low-k and ultra low-k dielectric materials in inter-metal dielectric (IMD) layers to reduce RC delay and parasitic capacitances. The general trend in IMD designs is that the dielectric constants (k) of the IMD layers tend to decrease from low-k regime to ultra low-k regime. This means that the IMD layers, in which metal lines and vias are formed, are more mechanically fragile. Further, the IMD layers may delaminate when under the stress caused by the thermal expansion. The bump cracking and delamination are particularly severe at the corners of IC chip 100. Although conventionally, underfill is used to fill the space between IC chip 100 and bump balls 104 in order to protect bump balls 104, bump cracking and delamination were still being observed.